Combining Haar Wavelet and Karhunen Loeve Transforms for Medical Images Watermarking

International audienceThis paper presents a novel watermarking method, applied to the medical imaging domain, used to embed the patient's data into the corresponding image or set of images used for the diagnosis. The main objective behind the proposed technique is to perform the watermarking of the medical images in such a way that the three main attributes of the hidden information (i.e. imperceptibility, robustness, and integration rate) can be jointly ameliorated as much as possible. These attributes determine the effectiveness of the watermark, resistance to external attacks and increase the integration rate. In order to improve the robustness, a combination of the characteristics of Discrete Wavelet and Karhunen Loeve Transforms is proposed. The Karhunen Loeve Transform is applied on the sub-blocks (sized 8x8) of the different wavelet coefficients (in the HL2, LH2 and HH2 subbands). In this manner, the watermark will be adapted according to the energy values of each of the Karhunen Loeve components, with the aim of ensuring a better watermark extraction under various types of attacks. For the correct identification of inserted data, the use of an Errors Correcting Code (ECC) mechanism is required for the check and, if possible, the correction of errors introduced into the inserted data. Concerning the enhancement of the imperceptibility factor, the main goal is to determine the optimal value of the visibility factor, which depends on several parameters of the DWT and the KLT transforms. As a first step, a Fuzzy Inference System (FIS) has been set up and then applied to determine an initial visibility factor value. Several features extracted from the Co-Occurrence matrix are used as an input to the FIS and used to determine an initial visibility factor for each block; these values are subsequently re-weighted in function of the eigenvalues extracted from each sub-block. Regarding the integration rate, the previous works insert one bit per coefficient. In our proposal, the integration of the data to be hidden is 3 bits per coefficient so that we increase the integration rate by a factor of magnitude 3

Etude de la conception d architectures matérielles dédiées pour les traitements multimédia (indexation de la vidéo par le contenu)

Cette thèse constitue une contribution à l étude de l indexation automatique de la vidéo par le contenu en vue de la conception d architectures matérielles dédiées à ce type d application multimédia. L indexation de la vidéo par le contenu présente un domaine de grande importance et qui est sans cesse en développement pour différents types d applications telles que l Internet, la TV interactive, les supports vidéo portables (PVR) et les applications de sécurité. L étude proposée est effectuée à travers des exemples concrets de techniques d analyse du contenu AV pour l indexation de la vidéo et selon différents aspects applicatifs, technologiques et méthodologiques. Elle s inscrit dans le cadre de la conception d architectures matérielles dédiées et de l exploitation des nouvelles technologies de systèmes embarqués pour les applications multimédia récentes. Un intérêt particulier est consacré à la technologie reconfigurable et aux nouvelles possibilités et moyens d utilisation des circuits FPGA. La première phase de cette thèse a été consacrée à l étude du domaine de l indexation automatique de la vidéo par le contenu. Il s agit de l étude des caractéristiques et des nouveaux besoins des systèmes d indexation au travers des approches et des techniques actuellement utilisées ainsi que les champs d application des nouvelles générations de ces systèmes. Ceci afin de montrer l intérêt d avoir recours à de nouvelles architectures et à de nouvelles solutions technologiques permettant de supporter les exigences de ce domaine. La deuxième phase de ce travail a été réservée à la validation et à l optimisation d un ensemble de descripteurs visuels de la norme MPEG-7 pour la segmentation temporelle de la vidéo. Ceci constitue une étude de cas par l étude d un exemple important de techniques d analyse du contenu AV utilisées dans une grande diversité d applications. L étude proposée constitue également une étape de préparation à l implémentation matérielle de ces techniques dans le contexte de conception d accélérateurs matériels pour l indexation automatique de la vidéo par le contenu en temps réel. Dans ce cadre différentes transformations algorithmiques ont été proposées dans le but d assurer une meilleure Adéquation Algorithme Architecture (AAA) et d améliorer les performances des algorithmes étudiés. La troisième phase de ce travail a été consacrée à l étude de la conception d opérateurs matériels dédiés pour les techniques d analyse du contenu AV ainsi qu à l étude de l exploitation des nouvelles technologies des systèmes reconfigurables pour la mise en œuvre de SORC pour l indexation automatique de la vidéo. Plusieurs architectures matérielles ont été proposées pour les descripteurs étudiés et différents concepts liés à l exploitation de la technologie reconfigurable et les SORC ont été explorés (méthodologies et outils associés pour la conception de tels systèmes sur puce, technologie et méthodes pour la reconfiguration dynamique et partielle, plateformes matérielles à base d FPGA, structure d un SORC pour l indexation de la vidéo par le contenu, etc.).This thesis constitutes a contribution to the study of content based automatic video indexing aiming at designing hardware architectures dedicated to this type of multimedia application. The content based video indexing represents an important domain that is in constant development for different types of applications such as the Internet, the interactive TV, the personal video recorders (PVR) and the security applications. The proposed study is done through concrete AV analysis techniques for video indexing and it is carried out according to different aspects related to application, technology and methodology. It is included in the context of dedicated hardware architectures design and exploitation of the new embedded systems technologies for the recent multimedia applications. Much more interest is given to the reconfigurable technology and to the new possibilities and means of the FPGA devices utilization. The first stage of this thesis is devoted to the study of the automatic content based video indexing domain. It is about the study of features and the new needs of indexing systems through the approaches and techniques currently used as well as the application fields of the new generations of these systems. This is in order to show the interest of using new architectures and technological solutions permitting to support the new requirements of this domain. The second stage is dedicated to the validation and the optimization of some visual descriptors of the MPEG-7 standard for the video temporal segmentation. This constitutes a case study through an important example of AV content analysis techniques. The proposed study constitutes also a stage of preparation for the hardware implementation of these techniques in the context of hardware accelerators design for real time automatic video indexing. Different Algorithm Architecture Adequacy aspects have been studied through the proposition of various algorithmic transformations that can be applied for the considered algorithms. The third stage of this thesis is devoted to study the design of dedicated hardware operators for video content analysis techniques as well as the exploitation of the new reconfigurable systems technologies for designing SORC dedicated to the automatic video indexing. Several hardware architectures have been proposed for the MPEG-7 descriptors and different concepts related to the exploitation of reconfigurable technology and SORC have been studied as well (methodologies and tools for designing such systems on chip, technology and methods for the dynamic and partial reconfiguration, FPGA based hardware platforms, SORC structure for video indexing, etc.).DIJON-BU Sciences Economie (212312102) / SudocSudocFranceF

Efficient BinDCT hardware architecture exploration and implementation on FPGA

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances

New Online DV-Hop Algorithm via Mobile Anchor for Wireless Sensor Network Localization

International audienceLocalization is a critical concern in many wireless sensor network (WSN) applications. Furthermore, correct information regarding the geographic placements of nodes (sensors) is critical for making the collected data valuable and relevant. Because of their benefits, such as simplicity and acceptable accuracy, the based connectivity algorithms attempt to localize multi-hop WSN. However, due to environmental factors, the precision of localisation may be rather low. This publication describes an Extreme Learning Machine (ELM) technique for minimizing localization error in range-free WSN. In this paper, we propose a Cascade Extreme Learning Machine (Cascade-ELM) to increase localization accuracy in Range-Free WSNs. We tested the proposed approaches in a variety of multi-hop WSN scenarios. Our research focused on an isotropic and irregular environment. The simulation results show that the proposed Cascade-ELM algorithm considerably improves localization accuracy when compared to previous algorithms derived from smart computing approaches. When compared to previous work, isotropic environments show improved localization results

Novel DV-hop algorithm-based machines learning technics for node localization in rang-free wireless sensor networks

International audienceLocalization is a critical concern in many wireless sensor network (WSN) applications. Furthermore, correct information regarding the geographic placements of nodes (sensors) is critical for making the collected data valuable and relevant. Because of their benefits, such as simplicity and acceptable accuracy, the based connectivity algorithms attempt to localize multi-hop WSN. However, due to environmental factors, the precision of localisation may be rather low. This publication describes an Extreme Learning Machine (ELM) technique for minimizing localization error in range-free WSN. In this paper, we propose a Cascade Extreme Learning Machine (Cascade-ELM) to increase localization accuracy in Range-Free WSNs. We tested the proposed approaches in a variety of multi-hop WSN scenarios. Our research focused on an isotropic and irregular environment. The simulation results show that the proposed Cascade-ELM algorithm considerably improves localization accuracy when compared to previous algorithms derived from smart computing approaches. When compared to previous work, isotropic environments show improved localization results

FPGA Implementation of Digital Images Watermarking System Based on Discrete Haar Wavelet Transform

In this paper we propose a novel and efficient hardware implementation of an image watermarking system based on the Haar Discrete Wavelet Transform (DWT). DWT is used in image watermarking to hide secret pieces of information into a digital content with a good robustness. The main advantage of Haar DWT is the frequencies separation into four subbands (LL, LH, HL, and HH) which can be treated independently. This permits ensuring a better compromise between robustness and visibility factors. A Field Programmable Gate Array (FPGA) that is based on a very large scale integration architecture of the watermarking algorithm is developed to accelerate media authentication. A hardware cosimulation strategy using the Matlab-Xilinx system generator (XSG) was applied to prove the validity of the suggested implementation. The hardware cosimulation results show the effectiveness of the developed architecture in terms of visibility and robustness against several attacks. The proposed hardware system presents also a high performance in terms of the operating speed